Embodiments of the invention relate to computer memory, and more specifically to three-dimensional (3D) stacked memory optimizations for latency and power.
High speed server systems with large memory capacities are becoming increasingly important in order to support ever growing customer demands. Modern portable devices require high capacity memory with low latency and a compact form factor. 3D memory stacking solutions can be utilized to provide higher capacity memory within a smaller footprint. The stacking of multiple memory integrated circuits (ICs), or chips, also provides an improvement in electrical performance due to shorter interconnects. One technique that is used to stack chips is referred to as through-silicon via (TSV) where vertical copper channels are built into each chip so that when they are placed on top of each other, the TSVs connect the chips together. TSVs allow for stacking of volatile dynamic random access memory (DRAM) devices with a processor to build very compact devices for portable applications. TSV techniques also allow 3D stacking of memory devices to create dense non-volatile memory such as flash or solid state drives with high capacity.